Job Description We’re looking for a passionate Staff Analog Design Engineer who is interested in designing analog and mixed-signal ICs for Power Management Products utilizing leading edge sub-micron BiCMOS /DMOS technologies. Products may include switching regulators, hot-swap eFuse, haft-bridge driver and power management ICs for fast growing markets such as networking, server, telecom, notebook/server core voltage, graphic card core regulator, point-of-load (PoL) and power modules. Responsibilities ? Analog Design Lead and architects to design IP blocks. ? Design analog circuits including but not limited to: LDO’s, Charge Pumps, Bandgaps, Amplifiers, Drivers, DAC’s, Current Sensing Techniques and other common precision circuits. ? Actively participates in the entire product development cycle, from product definition to product introduction (Trade-offs among Risk Assessment, Cost Analysis and Performance Evaluation) ? Design-For-Test strategic planning (Test Plan Development) to evaluate blocks’ performance ? Conduct design reviews and manage tape out schedule ? Provide guidance to layout engineers on critical analog implementation aspects, monitors progress of layouts, and closes the loop with post layout and simulation. ? Work with cross functional team to evaluate intended product behavior during pre Tape-out and post Tape-out. ? Design Blocks Verification (PVT, Monte Carlo Analysis), Top Level AMS Simulations and Post layout extraction and simulations ? Supervise and train juniors for successful design execution Preferred Qualification ? Requires BSEE/MSEE or Equivalent in Electrical Engineering ? 5+ years’ experience within analog design ? Comprehensive simulation skills in Cadence Environment ? Highly motivated individual and collaborative team player ? Strong analytical/problem-solving skills and Hands on experiments ? Solid background of BiCMOS & High Voltage BCD Process Technology, reliability, ESD Latch Up ? Strong knowledge of transistor level design and low power design techniques ? Solid understanding of control loop topologies (Constant On Time, Peak/Valley Current Mode, Voltage Mode control loops)